---------------------------------------------------------------------------------
  -- Design Name : Test Bench Clock
  -- File Name   : Clock.vhd
  -- Function    : Test Bench Clock
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use work.TBPkg.all;
use work.UserPkg.GenReg32;

entity Clock is
  port (
    clk : out std_logic := '0'
  );
end Clock;

architecture Clock_arch of Clock is
begin
  clk_process : process
  begin
    clk <= '1';
    wait for CLOCK_HALF_PERIOD;
    clk <= '0';
    wait for CLOCK_HALF_PERIOD;
  end process;
end Clock_arch;